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Silicon Labs /MGM240SB22VNA /RAC_S /PATRIM2

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Interpret as PATRIM2

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https://regviz.com/r/Silicon Labs/EFR32MG24A010F1024IM40/RAC_NS/PATRIM2#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (up_0pct)TX0DBMTRIMDUTYCYN 0 (dn_0pct)TX0DBMTRIMDUTYCYP 0 (up_0pct)TXPATRIM10DBMDUTYCYN 0 (dn_0pct)TXPATRIM10DBMDUTYCYP

TX0DBMTRIMDUTYCYN=up_0pct, TXPATRIM10DBMDUTYCYP=dn_0pct, TXPATRIM10DBMDUTYCYN=up_0pct, TX0DBMTRIMDUTYCYP=dn_0pct

Fields

TX0DBMTRIMDUTYCYN

TX0DBMTRIMDUTYCYN

0 (up_0pct): undefined

1 (up_1pct): undefined

2 (up_2pct): undefined

3 (up_3pct): undefined

4 (up_4pct): undefined

5 (up_5pct): undefined

6 (up_6pct): undefined

7 (na): undefined
TX0DBMTRIMDUTYCYP

TX0DBMTRIMDUTYCYP

0 (dn_0pct): undefined

1 (dn_1pct): undefined

2 (dn_2pct): undefined

3 (dn_3pct): undefined

4 (dn_4pct): undefined

5 (dn_5pct): undefined

6 (dn_6pct): undefined

7 (na): undefined
TXPATRIM10DBMDUTYCYN

TXPATRIM10DBMDUTYCYN

0 (up_0pct): undefined

1 (up_1pct): undefined

2 (up_2pct): undefined

3 (up_3pct): undefined

4 (up_4pct): undefined

5 (up_5pct): undefined

6 (up_6pct): undefined

7 (na): undefined
TXPATRIM10DBMDUTYCYP

TXPATRIM10DBMDUTYCYP

0 (dn_0pct): undefined

1 (dn_1pct): undefined

2 (dn_2pct): undefined

3 (dn_3pct): undefined

4 (dn_4pct): undefined

5 (dn_5pct): undefined

6 (dn_6pct): undefined

7 (na): undefined

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data